1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved oxide-nitride layer and a method for making the same.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to increase the drive current of transistors by reducing the threshold voltage, VT, necessary to activate the transistors. Several factors contribute to VT, one of which is the gate-to-substrate capacitance. In general, the higher the gate-to-substrate capacitance, the lower the VT of a transistor and hence, the higher the drive current. The value of this capacitance may be dependent upon the thickness of the gate dielectric arranged between the gate and substrate and the permittivity or dielectric constant, K, of the gate dielectric. In particular, the gate to substrate capacitance of a transistor is generally directly proportional to the permittivity of the gate dielectric. As such, the relative permittivity, or dielectric constant of a gate dielectric limits the amount of gate-to-substrate capacitance that can be achieved when a transistor is in operation. In addition, the gate to substrate capacitance of a transistor typically increases with decreasing gate dielectric thickness. As a result, the switching speed (from off to on and vice versa) of a transistor with a relatively thin gate dielectric is faster than a transistor with a relatively thick gate dielectric. Consequently, a transistor with a relatively thin gate dielectric requires a lower VT with which to activate the transistor.
Silicon dioxide is widely used as the gate dielectric material in semiconductor devices. However, the use of a silicon dioxide gate dielectric (hereinafter referred to as a “gate oxide”) may prevent a transistor from having a relatively low VT. In particular, the VT of a transistor with a silicon dioxide gate dielectric is limited by the relatively low dielectric constant of silicon dioxide, which is approximately 3.7 to 3.8. In addition, the use of very thin silicon dioxide gate dielectrics may present several problems. For example, thin silicon dioxide films may give rise to significant substrate leakage current when subjected to an electric field. More specifically, a gate oxide, which is less than approximately 20 angstroms thick, may be subject to what is known as the quantum mechanical tunneling effect. In such an effect, a tunneling current may undesirably flow between the semiconductor substrate and the gate conductor and pass through the gate oxide. It is postulated that these electrons may become entrapped within the gate oxide by dangling bonds, resulting in a net negative charge density in the gate oxide. As the trapped charge accumulates with time, VT of the transistor may shift from its design specification. Thin gate oxides may also be subject to breakdown due to defects commonly formed during the growth of thin gate oxides. In particular, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice. Such pinholes and voids may cause reliability failures within a transistor, for example. In addition, ultra thin gate oxides in p-type transistors may allow boron diffusion from the gate to the channel. Such diffusion may undesirably increase the VT of a transistor.
In addition, it is currently difficult to produce a gate oxide with a thickness less than 10 angstroms. In particular, the thickness and uniformity of an oxide layer that is less than 10 angstroms and is formed by conventional techniques is difficult to control across a semiconductor topography as well from wafer to wafer. Conventional processes typically include thermally growing a gate oxide upon a silicon substrate by a source of oxygen at a temperature of approximately 800° C. and approximately 900° C. The difficulty of growing a uniform, thin layer of oxide is primarily due to the rate of growth during such a process. In particular, it is often difficult to limit the growth of silicon oxide to 10 angstroms during such a process. In addition, the oxide layer is often subject to conditions, which allow the layer to continue to grow after completion of the thermal oxidation process. For example, significant oxide growth may occur while unloading wafers from the oxidation furnace. In some cases, the oxide layer may be subjected to conditions that allow an undesirable material to form on the oxide layer. In either case, such conditions (e.g., oxygen-containing atmospheres, heat, outgassing of storage containers) may be contained in further processing steps or during the transfer or storage of the semiconductor topography from one chamber to another.
As stated above, silicon dioxide is commonly used as a gate dielectric material in semiconductor devices. As such, the electrical properties of silicon dioxide at specific thicknesses may be well known. Due to the aforementioned problems associated with silicon oxide gate dielectrics, however, other materials are sometimes used for gate dielectrics. In some cases, it may be advantageous to describe the electrical properties of alternative materials in reference to the physical characteristics of silicon dioxide. In particular, it may be advantageous to describe the electrical properties, such as gate to substrate capacitance, of alternative materials in reference to the thickness of silicon dioxide including similar electrical properties. In such an embodiment, the alternative materials may be referred to as having an “electrically equivalent oxide thickness” as that of an oxide having a particular thickness. In other words, the alternative material may have electrical characteristics, which are similar to that of a certain thickness of silicon dioxide.
One alternative material used for gate dielectrics is an oxide-nitride stack. In such an embodiment, the gate dielectric may include a silicon nitride layer arranged upon and in contact with a silicon dioxide layer. Such a layer may be formed by thermally growing a silicon dioxide layer upon a substrate as described above and subsequently forming a nitride layer upon the oxide layer in a low-pressure chemical vapor deposition (LPCVD) chamber. The inclusion of nitride within a gate dielectric of a transistor may advantageously increase the gate-to-substrate capacitance of a transistor, and thereby decrease the VT of the transistor, since the dielectric constant of silicon nitride is approximately twice the dielectric constant of silicon dioxide. In this manner, the inclusion of nitride may advantageously decrease the electrical equivalent gate oxide thickness of a transistor. In addition, the higher dielectric constant of nitride may allow the gate dielectric to be thicker than a gate dielectric consisting entirely of silicon dioxide, thereby reducing substrate leakage current of the transistor. However, as the need to build integrated circuits faster and more complex increases, the thickness of oxide-nitride gate dielectrics needs to decrease. Unfortunately, the thicknesses of oxide-nitride gate dielectrics are limited by the thickness of the silicon dioxide layer. As explained above, the conventional process of thermally growing silicon oxide layers typically cannot form layers less than 10 angstroms. In addition, silicon oxide layers of less than 20 angstroms formed by such a process cause several problems, such as a lack of uniformity, a prevalent amount of defects, and quantum tunneling effects.
It would therefore be desirable to develop a method for fabricating an oxide-nitride layer with decreased thickness. It would further be desirable to use such a method for fabricating a transistor with an oxide-nitride gate dielectric having a low gate-to-substrate capacitance that is substantially resistant to gate dielectric breakdown. In addition, it may be advantageous to produce such a gate dielectric for a p-type transistor in which the diffusion of boron from the gate to the channel is significantly reduced.